Asic DV engineers

Job Description: You have an urgent opening for Design Verification (IP) for one of your clients in BLR location. The ideal candidate should have at least 5+ years of experience and be proficient in the following key skills: - Strong System Verilog (SV) and UVM expertise - Verification of PCIe Gen4/Gen5/Gen6 and/or CXL protocols (Mandatory) - Testbench development, Scoreboards, Assertions, Functional Coverage - Protocol debugging and regression analysis - Experience with VCS/Xcelium/Questa and Verdi If you are interested in this position, kindly share your updated profile to anand.arumugam@modernchipsolutions.com or contact 9900927620 for a detailed discussion. Job Description: You have an urgent opening for Design Verification (IP) for one of your clients in BLR location. The ideal candidate should have at least 5+ years of experience and be proficient in the following key skills: - Strong System Verilog (SV) and UVM expertise - Verification of PCIe Gen4/Gen5/Gen6 and/or CXL protocols (Mandatory) - Testbench development, Scoreboards, Assertions, Functional Coverage - Protocol debugging and regression analysis - Experience with VCS/Xcelium/Questa and Verdi If you are interested in this position, kindly share your updated profile to anand.arumugam@modernchipsolutions.com or contact 9900927620 for a detailed discussion.