Senior RTL Design Engineers

As a Senior RTL Design Engineer, your role will involve the following responsibilities: - Utilize your 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. - Demonstrate proficiency in writing clear and implementable micro-architecture specifications. - Showcase expertise in writing efficient RTL code in Verilog and SoC integration. - Possess a good understanding of assertions, coverage analysis, RTL synthesis, and timing closure. - Have prior experience working with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Engage in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce. - Display fluency in scripting languages like Perl and Python. - Have completed at least one tapeout. - Preferred experience in silicon bring-up and debug. Qualifications required for this position include: - 8 to 12 years of experience for candidates applying for the Bengaluru location and 12+ to 16 years of experience for candidates applying for the Hyderabad location. - Immediate to 30 days of notice period. - Relevant experience in RTL logic design, verification, synthesis, and timing optimization. - Proficiency in writing micro-architecture specifications and RTL code in Verilog. - Familiarity with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Exposure to scripting languages like Perl and Python. If you are interested in this opportunity, please share your updated profile to the provided email address or contact the mentioned phone number for further discussions. As a Senior RTL Design Engineer, your role will involve the following responsibilities: - Utilize your 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. - Demonstrate proficiency in writing clear and implementable micro-architecture specifications. - Showcase expertise in writing efficient RTL code in Verilog and SoC integration. - Possess a good understanding of assertions, coverage analysis, RTL synthesis, and timing closure. - Have prior experience working with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Engage in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce. - Display fluency in scripting languages like Perl and Python. - Have completed at least one tapeout. - Preferred experience in silicon bring-up and debug. Qualifications required for this position include: - 8 to 12 years of experience for candidates applying for the Bengaluru location and 12+ to 16 years of experience for candidates applying for the Hyderabad location. - Immediate to 30 days of notice period. - Relevant experience in RTL logic design, verification, synthesis, and timing optimization. - Proficiency in writing micro-architecture specifications and RTL code in Verilog. - Familiarity with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Exposure to scripting languages like Perl and Python. If you are interested in this opportunity, please share your updated profile to the provided email address or contact the mentioned phone number for further discussions.