Senior RTL Design Engineer

As a Senior RTL Design Engineer, your role will involve the following responsibilities and qualifications: Role Overview: You should have 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. Your expertise should include writing clear and implementable micro-architecture specifications. Proficiency in writing efficient RTL code in Verilog and SoC integration is essential. Additionally, you must possess a good understanding of assertions, coverage analysis, RTL synthesis, and timing closure. Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc., is required. Design bring-up and debug experience on FPGA-based emulation platforms such as HAPS, Veloce is preferred. Fluency in scripting languages like Perl and Python is a plus. Having completed at least one tapeout is mandatory, and silicon bring-up and debug experience is desirable. Key Responsibilities: - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization - Proficient in writing clear, implementable micro-architecture specifications - Expertise in writing efficient RTL code in Verilog and SoC integration - Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure - Working knowledge of interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Experience in design bring-up and debug on FPGA-based emulation platforms like HAPS, Veloce - Fluency with scripting languages (e.g., Perl, Python) - Must have gone through at least one tapeout - Preferred: Silicon bring-up and debug experience Qualifications Required: - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization - Proficiency in writing clear, implementable micro-architecture specifications - Expertise in writing efficient RTL code in Verilog and SoC integration - Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure - Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Experience in design bring-up and debug on FPGA-based emulation platforms like HAPS, Veloce - Fluency with scripting languages (e.g., Perl, Python) - Must have gone through at least one tapeout - Preferred: Silicon bring-up and debug experience If you are interested in this role, please share your updated profile to the provided email address or contact the recruiter for further discussion. As a Senior RTL Design Engineer, your role will involve the following responsibilities and qualifications: Role Overview: You should have 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. Your expertise should include writing clear and implementable micro-architecture specifications. Proficiency in writing efficient RTL code in Verilog and SoC integration is essential. Additionally, you must possess a good understanding of assertions, coverage analysis, RTL synthesis, and timing closure. Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc., is required. Design bring-up and debug experience on FPGA-based emulation platforms such as HAPS, Veloce is preferred. Fluency in scripting languages like Perl and Python is a plus. Having completed at least one tapeout is mandatory, and silicon bring-up and debug experience is desirable. Key Responsibilities: - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization - Proficient in writing clear, implementable micro-architecture specifications - Expertise in writing efficient RTL code in Verilog and SoC integration - Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure - Working knowledge of interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Experience in design bring-up and debug on FPGA-based emulation platforms like HAPS, Veloce - Fluency with scripting languages (e.g., Perl, Python) - Must have gone through at least one tapeout - Preferred: Silicon bring-up and debug experience Qualifications Required: - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization - Proficiency in writing clear, implementable micro-architecture specifications - Expertise in writing efficient RTL code in Verilog and SoC integration - Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure - Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Experience in design bring-up and debug on FPGA-based emulation platforms like HAPS, Veloce - Fluency with scripting languages (e.g., Perl, Python) - Must have gone through at least one tapeout - Preferred: Silicon bring-up and debug experience If you are interested