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About the role
4+ years of experience in Analog and mixed signal design Hands-on experience in designing analog blocks for Power management (voltage and current references, voltage detectors, linear and/or switching regulators) Hands-on experience in designing analog blocks for Clock management (oscillators, PLL, DLL) Hands-on experience in designing analog blocks for Signal processing (ADC, DAC) Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 28nm, 16nm and smaller. Should have hands-on experience in simulation of analog blocks, mixed-mode simulations, statistical simulations etc. Knowledge in scripting (PERL, TCL, etc.) and modelling (Matlab, VerilogA, etc.) tools will be an advantage Should have good insight into layouts Silicon debug/characterization experience is an advantage. Should possess good documentation, communication and presentation skills Work with the team to improve DV methodology and infrastructure Master Degree in Electrical/Electronics Engineering
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