RTL Engineer

Type: Full Time RTL Responsible for designing and implementing digital circuits at the level of logical operations and data transfers between registers, typically using hardware description languages like Verilog or VHDL. Develop RTL for logic blocks and participate in Front End activities like Synthesis, Timing Closure Asic implementation Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting Static Timing Analysis (STA) Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals Responsible for logic implementation of complex design block(s) using RTL coding techniques (Verilog) Code Verilog RTL for high performance designs with supervision from manager and input from peers and architects in the engineering team Must handle Verilog RTL logic design and debug Ability to work independently in team environment Minimum 4+ Years of experience in Computer architecture, micro-architecture, VLSI design and other design validation tool knowledge. Must have completed an BE OR B.Tech OR MS degree in Electronics Engineering or related/equivalent discipline. Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.