ASIC Design Verification Engineer

Role: ASIC Design Verification Engineer Location: San Jose, CA Duration: 6 + Months Job Description The ASIC Design Verification Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products. This role is a senior contributor focused on verifying highly complex ASICs that are used in these next-generation telecom systems and involves applying sophisticated verification techniques to perform advanced individual contributions to the projects. This engineer must be able to operate independently with minimal supervision in a fast-paced, dynamic, and highly technical environment. A successful candidate will be highly self-motivated, collaborative, with an open communication style. Knowledge of object-oriented (specifically C++) verification methodologies is required. A minimum of 7 years of experience are required. Must Have: 1. Experience with the latest ASIC verification methodologies, tools, and scripting/programming languages 2. Knowledge of & experience with C++ 3. Self-motivation and the ability to execute effectively without supervision Nice to have Qualifications: 1. Knowledge of System Verilog/UVM 2. Knowledge of DSP algorithms and modulation techniques such as QAM 3. Knowledge of Formal Verification methodologies. Thanks & Regards, Pavan Kumar| Jr.US IT Recruiter Thought wave Software and Solutions Desk: 6303810025 Email:pavan@thoughtwavesoft.com Website:www.thoughtwavesoft.com https://www.linkedin.com/in/pavan-kumar-madivada-416274170/