Design Verification Engineer, Santa Clara, CA

Job Title: Design Verification Engineer Duration: 6 Months Location: Santa Clara, CA, Report To Required SkillsBasic Qualifications Additional Skills: Can not be a sub-vendor candidate Job Description Apex Systems has an immediate opportunity for a skilled Design Verification Engineer to support one of our top clients based in Santa Clara, CA! This is a great way to get your foot in the door with a globally recognized leader in the cybersecurity industry! Please find the details below and send in your resume to apply! Duties: Responsibilities will include developing the verification environment; developing test plans and coding of test cases, analyzing regression failures and verifying the function of the ASIC at both the full chip and block level. Skills: Minimally, we are looking for someone with 1. Min 7+ years of DV experience, with several complete and successful ASIC design/verification cycles under his/her belt 2. Strong System Verilog/UVM, C/C++ and scripting skills The following is highly desirable - Ethernet 802. 3 expertise, third-party VIP integration, Ethernet MAC/PCS bring up. Thanks & Regards Syam B, 630-923-6952 syam@thoughtwavesoft.com