Design Engineer

Hands on with System Verilog and Assertion based verification methodology.Atleast 2years of experience on HVL (System Verilog,Vera,Specman,E,VMM,OVM,UVM).Knowledge of RTL coding styles.Low power verification (UPF/ CPF) would be an added plus Testbench architecture,coding and good understanding of design issues in RTL Experience on System C would be an added plus