Lead Verification Engineer

As a Senior Verification Engineer at this company, you will be involved in the verification of SOC level test benches and verification environments. Your responsibilities will include: - Working on SOC level test bench and verification environment - Designing test bench architecture, coding, and addressing design issues in RTL - Generating test benches, creating test vectors, performing simulations, and gate level simulations - Utilizing System Verilog and Assertion based verification methodology - Applying HVL such as System Verilog, Vera, Specman, E, VMM, OVM, UVM - Working independently, guiding team members, and leading a team of 5 or more engineers - Having experience with Verilog, EDA simulation, SV assertions, and test bench methodologies - Developing complex test benches in System Verilog using OVM/UVM methodology - Working on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB3, USB2, and Ethernet - Experience in formal verification - Demonstrating excellent written and oral communication skills Qualifications required for this position include: - 6 to 9 years of relevant experience - Education in BE/B-Tech (Electronics/ Electrical/ Electronics & Communication), MSc (VLSI/ Electronics/ Electrical/ Electronics & Communication), or preferred MS or MTech - Familiarity with simulation tools such as NCSIM, VCS, ModelSim, Questa - Knowledge of RTL coding styles would be advantageous - Experience in low power verification (UPF/CPF) and SystemC would be beneficial If you are interested in this opportunity, please email your resume to careers@truechip.net and mention the position/location in the subject line. As a Senior Verification Engineer at this company, you will be involved in the verification of SOC level test benches and verification environments. Your responsibilities will include: - Working on SOC level test bench and verification environment - Designing test bench architecture, coding, and addressing design issues in RTL - Generating test benches, creating test vectors, performing simulations, and gate level simulations - Utilizing System Verilog and Assertion based verification methodology - Applying HVL such as System Verilog, Vera, Specman, E, VMM, OVM, UVM - Working independently, guiding team members, and leading a team of 5 or more engineers - Having experience with Verilog, EDA simulation, SV assertions, and test bench methodologies - Developing complex test benches in System Verilog using OVM/UVM methodology - Working on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB3, USB2, and Ethernet - Experience in formal verification - Demonstrating excellent written and oral communication skills Qualifications required for this position include: - 6 to 9 years of relevant experience - Education in BE/B-Tech (Electronics/ Electrical/ Electronics & Communication), MSc (VLSI/ Electronics/ Electrical/ Electronics & Communication), or preferred MS or MTech - Familiarity with simulation tools such as NCSIM, VCS, ModelSim, Questa - Knowledge of RTL coding styles would be advantageous - Experience in low power verification (UPF/CPF) and SystemC would be beneficial If you are interested in this opportunity, please email your resume to careers@truechip.net and mention the position/location in the subject line.