RTL Design Engineer

Job Title: RTL Design Engineer Location: Bangalore Experience: 5+ Years Notice Period: Immediate to 30 Days Preferred. Job Description: We are seeking an experienced RTL Design Engineer with strong expertise in USB IP/subsystem design, RTL development, and SoC integration . Key Responsibilities: Design and implement RTL for USB IPs and subsystem components. Develop synthesizable RTL from architecture and microarchitecture specifications. Implement USB protocol features, power management, and performance enhancements. Work closely with verification, architecture, firmware, and physical design teams throughout the chip development cycle. Participate in design reviews and resolve RTL and integration issues. Support RTL verification, synthesis, timing closure, lint, CDC, and silicon bring-up activities. Optimize designs for performance, power, and area (PPA). Required Skills: 5+ years of RTL Design experience. Strong knowledge of Verilog and/or SystemVerilog. Hands-on experience designing USB 2.0, USB 3.x (SuperSpeed), or USB Type-C IPs. Strong understanding of USB Architecture and Protocol, Enumeration, Host/Device Communication, Control/Bulk/Interrupt/Isochronous Transfers, Link & Power Management, and Error Detection & Recovery. Experience with RTL Simulation, Debugging, and Waveform Analysis. Familiarity with Synthesis, Lint, CDC, STA, and Timing Constraints. Experience with Python, Perl, or Shell Scripting. Preferred Skills: Experience with USB Type-C and USB Power Delivery (USB-PD). Experience designing SoC interfaces using AXI/APB/AHB. Knowledge of Low-Power RTL Design Methodologies. Experience with Post-Silicon Debug and Hardware Bring-up. Strong understanding of the complete RTL development flow from Microarchitecture through Silicon.