RTL Design Engineer

Job Title: RTL Design Engineer Location: Bangalore Experience: 5+ Years Notice Period: Immediate to 30 Days Preferred. Job Description: We are seeking an experienced RTL Design Engineer with strong expertise in PCIe IP and subsystem design, RTL development, and SoC integration. Key Responsibilities: Design and develop RTL for PCIe IPs and subsystem components. Translate architecture and microarchitecture specifications into high-quality RTL using Verilog/SystemVerilog. Implement PCIe protocol features, performance optimizations, and low-power functionality. Collaborate with architecture, verification, physical design, and firmware teams throughout the development cycle. Participate in design reviews, code reviews, and microarchitecture discussions. Debug functional issues during simulation, emulation, and post-silicon bring-up. Support synthesis, timing closure, lint, CDC, and design signoff activities. Required Skills: 5+ years of RTL Design experience. Strong knowledge of Verilog and/or SystemVerilog. Hands-on experience designing PCIe Gen3/Gen4/Gen5 IP or subsystem components. Strong understanding of PCIe architecture, including LTSSM, Link Training, TLP/DLLP Processing, Configuration Space, MSI/MSI-X, and Error Detection & Recovery. Experience with RTL Debugging, Simulation, and Waveform Analysis. Familiarity with Lint, CDC, Synthesis, and Timing Constraints. Experience with Python, Perl, or Shell Scripting. Preferred Skills: Experience with High-Speed SoC or Networking/Datacenter Silicon. Knowledge of AMBA Protocols (AXI/AHB/APB). Experience with Low-Power Design Methodologies (UPF/CPF). Exposure to Post-Silicon Bring-up and Performance Optimization.