FPGA Engineer - RTL (Verilog/VHDL), Synthesis

As an FPGA Engineer specializing in RTL design using Verilog/VHDL, your role will involve the following key responsibilities: - Strong experience with Xilinx/Altera boards and software, demonstrating proficiency in VHDL/Verilog. - Utilize strong lab/debug skills including JTAG/SWD, logic analyzers, oscilloscopes, and power/current measurement for issue reproduction and root cause analysis. - Exhibit expertise in SoC fabrics and protocols such as AXI/AHB/APB, clock/reset domains, CDC, and timing constraints (SDC/XDC). - Implement digital interface protocols like SPI, I2C, UART, etc., and possess good understanding of verification environments and test creation. - Prior experience with Arm MPS3 or similar FPGA-based Arm evaluation platforms is highly beneficial. - Additional advantages include experience with ARM or RISC-V MCU/CPU design integration, knowledge of JTAG, scan, TAP, testing architectures, Ethernet and/or USB design. Your qualifications for this role should include: - 3-5 years of experience in RTL design with proficiency in Verilog/VHDL and synthesis. - Familiarity with FPGA development tools and platforms, particularly Xilinx/Altera. - Strong understanding of SoC architectures, digital interface protocols, and verification methodologies. - Prior exposure to Arm MPS3 or similar FPGA-based Arm evaluation platforms would be advantageous. Please note that the job location for this role is Bengaluru. As an FPGA Engineer specializing in RTL design using Verilog/VHDL, your role will involve the following key responsibilities: - Strong experience with Xilinx/Altera boards and software, demonstrating proficiency in VHDL/Verilog. - Utilize strong lab/debug skills including JTAG/SWD, logic analyzers, oscilloscopes, and power/current measurement for issue reproduction and root cause analysis. - Exhibit expertise in SoC fabrics and protocols such as AXI/AHB/APB, clock/reset domains, CDC, and timing constraints (SDC/XDC). - Implement digital interface protocols like SPI, I2C, UART, etc., and possess good understanding of verification environments and test creation. - Prior experience with Arm MPS3 or similar FPGA-based Arm evaluation platforms is highly beneficial. - Additional advantages include experience with ARM or RISC-V MCU/CPU design integration, knowledge of JTAG, scan, TAP, testing architectures, Ethernet and/or USB design. Your qualifications for this role should include: - 3-5 years of experience in RTL design with proficiency in Verilog/VHDL and synthesis. - Familiarity with FPGA development tools and platforms, particularly Xilinx/Altera. - Strong understanding of SoC architectures, digital interface protocols, and verification methodologies. - Prior exposure to Arm MPS3 or similar FPGA-based Arm evaluation platforms would be advantageous. Please note that the job location for this role is Bengaluru.