Source description
About the role
Job Description: You should possess excellent communication skills and exhibit a strong willingness to tackle various challenges. Your responsibilities will include working with large FPGA development flow and tools on Xilinx devices. You are required to have experience in wireless communication and proficiency in Verilog RTL language. Additionally, you should be well-versed in Xilinx's build flow, covering design entry in Verilog, synthesis, place and route, timing constraints, and timing closure. Key Responsibilities: - Hands-on experience with lab FPGA debug methodologies. - Proficiency in using lab debug equipment such as oscilloscopes and logic analyzers. - Familiarity with verification methodologies, RTL and gate-level simulations, and debug. - Experience in debugging silicon and PCB issues. - Running basic verification tests on simulations. Qualifications Required: - Skills in FPGA, RTL, Verilog, and Avionics. - Location: Hyderabad - Experience: 8 - 15 Years Job Description: You should possess excellent communication skills and exhibit a strong willingness to tackle various challenges. Your responsibilities will include working with large FPGA development flow and tools on Xilinx devices. You are required to have experience in wireless communication and proficiency in Verilog RTL language. Additionally, you should be well-versed in Xilinx's build flow, covering design entry in Verilog, synthesis, place and route, timing constraints, and timing closure. Key Responsibilities: - Hands-on experience with lab FPGA debug methodologies. - Proficiency in using lab debug equipment such as oscilloscopes and logic analyzers. - Familiarity with verification methodologies, RTL and gate-level simulations, and debug. - Experience in debugging silicon and PCB issues. - Running basic verification tests on simulations. Qualifications Required: - Skills in FPGA, RTL, Verilog, and Avionics. - Location: Hyderabad - Experience: 8 - 15 Years
More at Vitestork Consulting
Related open roles
ASIC RTL Design Lead - Verilog/SystemVerilog, CDC, Lint - [ID 014]
Delhi NCR
Chip Lead / SoC Design Leader
Bangalore
Senior Principal Solution Engineer (Noida)
Delhi NCR
Chip Lead / SoC Design Leader
Delhi NCR
Pre-Silicon System Performance Staff Engineer - [ID 018]
Bangalore
FPGA Engineer - RTL (Verilog/VHDL), Synthesis
India