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- Lead DFT Engineer - ATPG , SCAN - [ID 014] Job Description Define and drive the overall DFT strategy for complex SoC/ASIC projects. Lead DFT architecture discussions and provide guidance to design teams across multiple sites. Implement and verify various DFT techniques such as: Scan insertion (full/partial scan) Boundary scan (IEEE 1149.1) MBIST (Memory BIST) LBIST (Logic BIST) JTAG integration ATPG (Automatic Test Pattern Generation) Collaborate with RTL, physical design, and verification teams to ensure seamless integration of DFT features. Perform DFT verification, including fault simulation and coverage analysis. Work closely with test engineering teams for test pattern bring-up and debug on ATE. Ensure testability requirements are met and align with manufacturing and yield expectations. Mentor junior engineers and establish best practices and DFT methodologies. Own DFT docu Skills: Scan insertion , MBIST, LBIST, JTAG Job Location: Bangalore, Hyderabad, Ahmedabad, Noida Experience: 8 - 15 Yrs Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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