Lead Digital Verification Engineer - SOC

Job Description - Masters in Electronics Engineering (a relevant experience with minimum 4 years in a semiconductor or high technology RD environment would be appreciated) - Experience in Hardware Design Language (such as VHDL or Verilog). - Experience in Digital verification with various skill sets: (a) Universal Verification Methodology (UVM) (b) System Verilog (SV) (c) C/C++ language, preferably with ARM CORTEX processor (d) Formal Methodology (Jasper GOLD) (e) Scripting languages (PERL, TCL, PYTHON) - Good communication and written skills in English. - Able to work in a multi-cultural team. - Strong analytical and problem-solving skill. -Able to keep up with fast moving new verification methodology. Skills: UVM, SV, C / C++, ARM Processors Experience: 7 - 12 years Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.