Source description
About the role
- RTL Design Engineer - [ID 017] Job Description BSEE and at least 3 years of prior RTL develop experience required. MSEE and at-lest 1 years of prior RTL experience strongly preferred. Prior experience RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts. Strong ability on RTL debug , and logic development. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of synthesis, STA, design for test, and design methodologies Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Strong background in Constraint analysis and debug, using industry standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing. Team player with a passion to innovate and can-do attitud Skills: DDR/GDDR DRAM protocol; high-speed PHYs Job Location: Bengaluru Experience: 3 - 6 Yrs Company Name: EDA Semiconductor RD Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
More at Vitestork Consulting