STA / Synthesis - Staff / Sr. Staff / Lead / Principal / Manager

Job Description In this position, you will be responsible for all aspects of STA and timing closure activities of SoCs in lower technology nodes. Design and Architecture understanding, Interaction with FE,DFT, Verification teams, Clocking, Constraints development, ACIO Timing Understanding on synchronous and asynchronous paths, Clock domain crossing issues, Understanding and debugging extraction issues Deciding timing signoff modes and corners, Design margins, Hierarchical timing including IO budgeting for partitions, Drive the designs to timing closure Interacting, supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff and quality checks. You will also be part of debug, troubleshoots for a wide variety of tasks up to and including difficult Skills: STA, Synthesis Experience: 4 - 20 yrs