VLSI Developer

Tirupathi Upto 2.4LPA 0-1 Yr Apply Now Verilog/VHDL for FPGA implementations. Xilinx Vivado IPs and other FPGA toolchains. DSP algorithms for image and signal processing. MATLAB/Simulink for algorithm modeling and hardware mapping. communication protocols (I2C, SPI, UART, PCIe, AXI, etc.). students and Ph.D. scholars in developing VLSI-based academic projects. MATLAB/Simulink for DSP applications. communication protocols (AXI, PCIe, Ethernet, etc.). ASIC design flow and RTL-to-GDSII concepts. AI/ML accelerators on FPGA (optional but a plus). mentoring students and guiding research projects. Work Type : Work from office Roles & Responsibilties : Develop RTL code using Verilog/VHDL for FPGA implementations. Optimize hardware designs for performance, area, and power. Work on Xilinx Vivado IPs and other FPGA toolchains. Implement and optimize DSP algorithms for image and signal processing. Work with MATLAB/Simulink for algorithm modeling and hardware mapping. Perform functional and timing verification using UVM, SystemVerilog . Develop testbenches, run simulations, and analyze waveforms. Conduct post-synthesis and post-layout verification. Implement and verify standard communication protocols (I2C, SPI, UART, PCIe, AXI, etc.). Integrate and validate external peripherals in FPGA-based designs. Guide students and Ph.D. scholars in developing VLSI-based academic projects. Provide documentation, reports, and technical support for research work. Deliver workshops and training sessions on VLSI, FPGA, and Signal Processing . Requirements : B.Tech/M.Tech/Ph.D. in VLSI, Electronics, Electrical, or a related field . Strong experience in RTL design (Verilog/VHDL) . Hands-on experience with FPGA toolchains (Xilinx Vivado, Quartus, etc.) . Knowledge of MATLAB/Simulink for DSP applications. Expertise in verification methodologies (UVM, SystemVerilog, ModelSim, QuestaSim) . Familiarity with communication protocols (AXI, PCIe, Ethernet, etc.). Experience in hardware debugging and timing analysis. Experience in HLS (High-Level Synthesis) . Knowledge of ASIC design flow and RTL-to-GDSII concepts. Exposure to AI/ML accelerators on FPGA (optional but a plus). Passion for mentoring students and guiding research projects.