Senior ASIC / RTL / Logic Design Engineer Memory Controller Design

As a Senior ASIC / RTL / Logic Design Engineer at our Memory Controller Design Centre of Excellence, you will have the opportunity to architect and implement high-performance memory controller IP for cutting-edge AI compute platforms. Your responsibilities will include: - Designing and delivering standards-compliant, production-ready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers, optimized for AI-centric server SoCs operating at 9600 Mbps to 14400 Mbps and beyond. - Developing architecture, microarchitecture, and detailed design specifications tailored for AI compute workloads to ensure best-in-class performance, power efficiency, and area (PPA). - Enhancing ASIC development flows using advanced EDA tools, automation, and scripting (Python, Perl, TCL) to support rapid iteration cycles for AI-focused silicon. - Implementing complex RTL design blocks in Verilog/SystemVerilog following robust design methodologies suitable for high-bandwidth, low-latency AI accelerators. - Performing functional simulation, performance modeling, and debug to validate correctness and throughput under AI-oriented traffic patterns. - Demonstrating a strong understanding of Lint, CDC, Synthesis, Power Analysis, STA constraints, and LEC for high-frequency, high-reliability server-class designs. - Defining and optimizing timing constraints to meet aggressive frequency targets typical of AI compute architectures. - Identifying, tracking, and resolving design bugs across the development lifecycle using industry-standard tracking systems. - Collaborating closely with verification, physical design, architecture, and firmware teams to ensure seamless integration into AI-centric server chip platforms. - Participating in design reviews, code reviews, and technical discussions to drive continuous improvement in design quality and methodology. - Mentoring junior engineers to foster a culture of technical depth, innovation, and excellence. Key Qualifications: - B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI, or related field from a reputed institution. - 10+ years of hands-on experience in ASIC design, RTL development, and logic design for complex SoCs or IP subsystems. - Strong expertise in Verilog and SystemVerilog, with deep knowledge of digital design fundamentals, memory subsystems, and high-speed interfaces. - Proven experience with Lint, CDC, Synthesis, Power Analysis, STA, and LEC tools (Synopsys, Cadence, Mentor). - Experience working on server-class, high-performance, or AI-accelerator SoCs is a strong plus. - Excellent analytical, debugging, and problem-solving skills with the ability to thrive in a fast-paced, product-focused environment. - Strong communication and collaboration skills for working with cross-functional global engineering teams. Please note that the above job description is for the role of Senior ASIC / RTL / Logic Design Engineer at our Memory Controller Design Centre of Excellence. As a Senior ASIC / RTL / Logic Design Engineer at our Memory Controller Design Centre of Excellence, you will have the opportunity to architect and implement high-performance memory controller IP for cutting-edge AI compute platforms. Your responsibilities will include: - Designing and delivering standards-compliant, production-ready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers, optimized for AI-centric server SoCs operating at 9600 Mbps to 14400 Mbps and beyond. - Developing architecture, microarchitecture, and detailed design specifications tailored for AI compute workloads to ensure best-in-class performance, power efficiency, and area (PPA). - Enhancing ASIC development flows using advanced EDA tools, automation, and scripting (Python, Perl, TCL) to support rapid iteration cycles for AI-focused silicon. - Implementing complex RTL design blocks in Verilog/SystemVerilog following robust design methodologies suitable for high-bandwidth, low-latency AI accelerators. - Performing functional simulation, performance modeling, and debug to validate correctness and throughput under AI-oriented traffic patterns. - Demonstrating a strong understanding of Lint, CDC, Synthesis, Power Analysis, STA constraints, and LEC for high-frequency, high-reliability server-class designs. - Defining and optimizing timing constraints to meet aggressive frequency targets typical of AI compute architectures. - Identifying, tracking, and resolving design bugs across the development lifecycle using industry-standard tracking systems. - Collaborating closely with verification, physical design, architecture, and firmware teams to ensure seamless integration into AI-centric server chip platforms. - Participating in design reviews, code reviews, and technical discussions to drive continuous improvement in design quality and methodology. - Mentoring junior engineers to foster a culture of technical depth, innovation, and excellence. Key Qualifications: - B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI, or r