Silicon Validation Director

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency unlocking unprecedented efficiency for AI training and inference at scale . our architecture is not just an incremental improvement its a foundational shift in how AI hardware is built for the futur e. Silicon Validation Direc torLocation: Hydera bad Department: Silicon Engineering / Hardware Valida tionEmployment Type: Full- Time We are a semiconductor company pioneering high-performance interconnect and chip-tochip communication solut ions.Our engineering teams push the boundaries of what is possible in silicon design, validation, and system integra tion.We are looking for a seasoned Silicon Validation Lead to join our R&D organization and drive end-to-end validation of complex SoC platf orms. Role Ov erview As the Silicon Validation Director you will own the full lifecycle of silicon bring-up and validation for next-generation SoC platforms that integrate PCIe, CXL, DDR5, RISC-V processors, Memory Fabric, PCIe Switch, and Caliptra Root of Trust (RoT) subs ystems. You will lead a cross-functional validation team, define test strategies, and act as the primary technical interface between design, architecture, firmware, and system teams to ensure first-pass silicon quality and robust production re adiness. Key Respons ibilitiesSilicon Bring-Up & Validation Lead pre- and post-silicon validation for complex SoCs encompassing PCIe Gen 4/5/6, CXL 1.1/2.0/3.0, DDR5 memory subsystems, RISC-V processor cores, Memory Fabric, PCIe Switch, and Caliptr a RoT IP. Drive silicon bring-up from power-on through full functional validation, characterization, and compliance testing. Develop and own comprehensive silicon validation plans, test coverage matrices, and sign-off criteria aligned with tapeout and production m ilestones. Execute and manage compliance and interoperability testing against PCIe, CXL, JEDEC DDR5, and relevant security/RoT standards. Test Architecture &am p; Strategy Define test infrastructure architecture: board-level bring-up environments, FPGA prototypes, simulation correlation, and lab automation frameworks. Drive development of validation collateral including test plans, test suites, regression frameworks, and pass/fail criteria for all integrate d subsystems. Establish coverage tracking dashboards and triage processes to systematically reduce validation escapes. Debug & Root Cause Analysis Lead deep-dive debugging of complex multi-layer failures spanning RTL, firmware, hardware, and system software. Utilize protocol analyzers, logic analyzers, oscilloscopes, and CXL/PCIe test equipment (e.g., Teledyne LeCroy, Keysight, Spirent) to isolate and chara cterize issues. Author and maintain detailed bug reports, failure analysis documents, and errata for silicon revisions. Team Leadership &am p; Collaboration Lead and mentor a team of validation engineers; set technical direction, review deliverables, and foster a culture of e ngineering rigor. Collaborate closely with RTL design, DV, firmware, and software teams to ensure seamless hand-off from pre-silicon simulation to physical s ilicon validation. Interface with external IP vendors, OEM/ODM partners, and compliance labs for interoperability and certif ication activities. Represent the validation team in architecture reviews, design reviews, and program planning meetings. Process & Co ntinuous Improvement Champion test automation and CI/CD integration for r egression management. Drive lessons-learned processes across silicon spins and contribute to validation met hodology improvements. Establish and maintain lab safety, equipment inventory, and test asset man agement best practices. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Sc ience, or related field. 18+ years of hands-on silicon validation or hardware validation engineering experience, with at least 6 years in a Manager/ Lead or staff-level role. Deep expertise in PCIe (Gen 4/5/6): protocol-level knowledge, compliance testing, physical layer ch aracterization, and debug. Strong hands-on experience with CXL (1.1 / 2.0 / 3.0): memory semantic protocols, device types (Type 1/2/3), coherency mechanisms, an d interoperability testing. Extensive experience validating DDR5 memory subsystems: timing margins, signal integrity, JEDEC c ompliance, and RAS features. Solid experience .