Staff Physical Design IR / EM Engineer

Physical Design IR / EM Engineer (Mid to Senior Level) Location: Bengaluru, India Experience: 5-15 years Industry: Semiconductors | AI | Networking | ASIC Design Role Overview We are looking for a hands-on IR-drop and Electromigration (EM) engineer to run power-integrity and reliability sign-off across our AI-networking SoCs. You will build and run static/dynamic IR-drop and EM analysis at block, partition, and full-chip level, diagnose violations, and partner with PD and PDN teams to close power-integrity and reliability goals at advanced nodes. Key Responsibilities IR-Drop Analysis: Set up and run static and dynamic IR-drop analysis at block, partition, and full-chip levels, and drive results to sign-off targets.EM Sign-off: Run signal and power EM analysis, identify violations, and drive fixes with PD implementation teams.Power Grid Support: Support PDN/power-grid design, decap planning, and PG mesh tuning to meet IR-drop and power-integrity specifications.Violation Debug: Root-cause IR and EM hotspots and recommend floorplan, power-grid, or placement changes to resolve them.Vectorless & Vector-Based Flows: Run both vectorless and activity/vector-based dynamic analysis and correlate with realistic switching scenarios.Cross-Functional Closure: Coordinate with PD, STA, packaging, and foundry teams to apply technology rules and meet reliability criteria at tape-out.Reporting & Sign-off: Generate clear IR/EM status reports and drive blocks and full chip through power-integrity sign-off.Automation: Contribute scripts to reduce IR/EM analysis turnaround time and improve accuracy.Key Skills IR/EM Tools: Hands-on expertise with Ansys RedHawk-SC and/or Cadence Voltus for static/dynamic IR-drop and EM analysis.Power Integrity: Solid understanding of power-grid design, PDN concepts, decap strategy, and dynamic voltage-drop mechanisms.EM Fundamentals: Strong grasp of signal and power EM physics, current-density rules, and foundry reliability requirements.PD Fundamentals: Working knowledge of floorplanning, placement, routing, and how implementation choices impact power integrity.Scripting: Proficiency in Python and/or Perl/TCL for analysis automation and reporting.Process Technology: Hands-on experience on advanced FinFET nodes (7nm/5nm and below).Problem-Solving: Strong analytical and debugging skills to independently root-cause and resolve power and reliability issues.Communication: Good communication skills to clearly articulate sign-off status across PD, analog, integration, and foundry teams.Preferred Qualifications Bachelors or Masters in Electrical Engineering, Computer Engineering, or a related field.Experience with full-chip power-integrity sign-off on large, high-performance designs.Familiarity with multi-die / chiplet power delivery and package-aware IR analysis.Exposure to ESD/latch-up concepts and Calibre PERC flows is a plus. .